1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Description of the Related Art
In recent years, electrically erasable nonvolatile semiconductor storage devices (nonvolatile memories), such as EEPROMs (Electrically Erasable and Programmable ROMs), have been in increasing demand. Each memory cell in the nonvolatile memory is structured such that a tunnel insulating film, a floating gate, an inter-electrode insulating film and a control gate are stacked in sequence on a semiconductor substrate.
With the nonvolatile memory, to lower the operating voltage of each memory cell, it is important to increase the ratio C2/ (C1+C2), where C2 is the capacitance of the upper capacitor formed between the floating gate and the control gate and C1 is the capacitance of the lower capacitor formed between the semiconductor substrate and the floating gate.
To increase the capacitance ratio (coupling ratio), a structure such that the floating gate is made larger in the width of the top surface than in the width of the bottom surface (reverse tapered structure) and a structure such that the floating gate is covered on top and side surfaces with an inter-electrode insulating film have been proposed. However, combining these structures results in the following problems.
To obtain the abovementioned structures, it is required to form the control gate film between adjacent floating gate films processed into the reverse tapered form. However, it is difficult to completely form the control gate film in the area between the floating gate films because of their reverse tapered structure. This will lead to degraded device characteristics and lowered reliability.
For example, Japanese Unexamined Patent Publications Nos. 8-316348 and 2002-22008 describe nonvolatile semiconductor storage devices having floating gates of the reverse tapered structure but disclose no solution to the above problems.
As described above, in order to increase the coupling ratio (C2/(C1+C2)) of the upper capacitor and the lower capacitor there have been proposals to form the floating gate into the reverse tapered shape or cover the floating gate with the inter-electrode insulating film on the top and side surfaces. However, difficulties are involved in completely forming the control gate in the area between floating gates, causing degraded device characteristics and lowered reliability.